Cmos Power Device Modeling and Amplifier Circuits By

A power amplifier (PA) is a key part of the RF front-end in transmitters for a local broadband network. Today, commercial PAs are made of III-V HEMT and HBT technology with excellent results. An integrated system-on-chip power amplifier circuit using CMOS technology for cost-effective and spectrum-efficient high-speed wireless communication presents major challenges because power amplifiers have been the limiting components in RF CMOS transmitter integrated circuits (ICs). At high frequencies, the distributed effect and power device-scaling issues put other constraints on PA design such as the trade-off between output power (P out) and power added efficiency (PAE). Recently, CMOS has become attractive for low-cost and high-level integration due to the advancement of NMOS performance with f t and f max > 100 GHz and is available from commercial CMOS foundries. However, the foundry-provided BSIM-RF model is unable to accurately predict the I-V characteristics and RF behaviors (f t and f max) of power devices with widths of several hundred microns. Therefore, an advanced large-signal model which is able to predict distributed nonlinear effects is crucial for the successful design of high-frequency PAs. The microwave lumped and distributed layout parasitic effect in the 130 nm (BSIM3v3-RF) and 90 nm (BSIM4-RF) models to accurately predict gain, output power, and harmonic distortions of power MOSFETs at millimeter wave frequencies. The proposed power device model is verified for single devices as well as for the integrated power amplifier circuits in S-band and W-band applications. For S-band WiMAX application, we have developed an accurate modeling with layout parasitic of power CMOS devices and designed lossless matching networks to achieve single-end PA performance of 31 dB gain, 21.4 dBm output power, and 14.5% PAE at the 1 dB compression point. The measured maximum output power is 25.5 dBm and the associated PAE is 32%. For W-band application, a compact two-stage CMOS power amplifier is designed iii with gain boosting at the common gate transistor, source degeneration for the cascode devices and LC short stub matching networks. The amplifier was fabricated and demonstrated with excellent RF performance of 18 dB gain, 10.8 dBm linear output power, 13.3 dBm saturated power, and 11.8% PAE at 80 GHz with a minimum chip area of 0.35 mm 2 in 90 nm CMOS technology. Monolithic power-combining techniques are attractive for delivering linear power over 20 dBm at W-band range due to the size reduction of the combiner. A W-band monolithic CPW …